FIG. 1 diagrammatically shows a memory plane MEM of the above-mentioned type that conventionally includes word lines WLi and columns COLj, each including two bit lines BL0 and BL1.
The memory cells in such a memory plane, not shown in FIG. 1 for simplification reasons, are differentially connected between two bit lines BL0 and BL1 in each column in the memory plane and may be activated by a word line WLi.
Moreover, read amplifiers SA are arranged at the bottom of columns in the memory plane and are conventionally activated by an activation signal output by control means MC.
A memory cell in the memory plane is shown in FIG. 2. This cell includes a first inverter InvA and a second inverter InvB connected back to front between a first node A and a second node B. Each inverter InvA and InvB is composed of an nMos transistor, N0 and N1 respectively, and a pMos transistor, P0 and P1 respectively. A first access transistor TA is provided, of which a drain is connected to node A, a gate is connected to a word line WL in the memory plane, and a source is connected to a first bit line BL0. A second access transistor TB is also provided, of which a drain is connected to node B, a gate is connected to the word line WL and a source is connected to the second bit line BL1 of the memory cell column.
A memory cell in a column of memory cells in the memory is programmed by applying a potential Vdd onto the word line WL associated with the cell to be programmed, and depending on the data 0 or 1 to be programmed in the selected cell, a zero potential (connection to the ground) or the potential Vdd is applied onto the first bit line BL0, and a potential inverse to the potential applied to the line BL0 is applied to the second bit line BL1. For example, to program a logical 0 in the memory cell in FIG. 2, VDD is applied on line WL and on line BL1, and line BL0 is connected to the ground.
During a read operation of this memory cell, the two lines BL0 and BL1 are precharged to a power supply potential Vdd, and the corresponding word line WL is set to potential Vdd to select the memory cell in read (the other word lines being connected to the ground). The word line WL is at the high potential, therefore the access transistors TA and TB of the cell are conducting. According to the example, since node A is equal to 0 and line BL0 is precharged at Vdd, a current circulates through the channel of the access transistor TA which will discharge the line BL0 and progressively sets its potential to 0. On the other hand, node B in the memory cell and the bit line BL1 are at the same potential, the line BL1 is assumed to remain in its high precharge state, namely at the potential Vdd (in fact this other bit line may nevertheless be set to ground due to parasite leakage currents from other memory cells connected to this other bit line, but processing of this parasite behavior is not the subject of the present application).
The amplifier SA arranged at the bottom of the memory column with its two differential inputs connected to the first bit line BL0 and to the second bit line BL1 respectively, will then detect a potential difference between lines BL0 and BL1 after a certain time due to the progressive discharge of line BL0, and consequently will produce data corresponding to the data memorised in the memory cell, namely a logical 0 according to the example.
Due to the intrinsic characteristics of the transistors forming a read amplifier SA, it is essential that the read amplifier SA in the memory should be activated at a specific time of the read operation so that signals applied to the inputs enable the amplifier to correctly detect the potential difference expected between the two bit lines BL0 and BL1 and thus obtain the good read value. More precisely, the differential amplifier SA located at the bottom of the column needs to be activated when the potential of the bit line discharging during reading is low enough so that the potential difference between the two bit lines is greater than the input offset voltage of the amplifier (this offset voltage corresponding to the threshold starting from which the read amplifier is capable of amplifying the data from the memory point read without error, is due to variation of production parameters).
Consequently, the memory is normally equipped with a dummy path referenced CHdum in FIG. 1, designed to self adjust the time at which the control means MC output the signal to activate the read amplifiers arranged at the bottom of the memory plane columns.
This dummy path includes a dummy column formed from two dummy bit lines DBL0 and DBL1. Dummy memory cells CELDi are connected to this dummy column, of which at least one of them referenced CLD1 is activated by a dummy word line DWL.
The dummy memory cell CELD1 activated by the dummy word line DWL is programmed so as to discharge (set to the ground) at least one of the dummy bit lines DBL0 and DBL1. The dummy bit line that will be discharged when the dummy cell CELD1 is activated, is then used in a manner known per se, to generate the read amplifiers activation signal Act in the memory plane through the control means MC. As an example embodiment, the dummy bit line (or the two dummy bit lines connected together when the discharge of the two dummy bit lines is used to generate the activation signal) is connected to the input of an inverter (not shown) provided within the control means MC to output the activation signal Act.
In practice, several dummy memory cells CELD1 to CELDn can be activated by the word line DWL so as to produce a discharge of the dummy bit line(s) that takes place more quickly than the discharge from a standard bit line BLT of a column in the memory plane.
FIG. 3 shows an example of a dummy memory cell CELDn configured to discharge the two dummy bit lines DBL0 and DBL1 of the dummy path when it is activated by DWL for the purpose of generating the signal to activate memory plane read amplifiers. The dummy memory cell includes four memory transistors N4/P4 and N5/P5, each pair of transistors in series, N4/P4 and N5/P5 respectively, forming a first and a second inverter and two access transistors N2 and N3. The first access transistor N2 has its drain connected to the output from inverter N4/P4, its gate connected to the dummy word line DWL and its source connected to the dummy bit line DBL1. The second access transistor N3 has its drain connected to the output from the inverter N5/P5, its gate connected to the dummy word line DWL and its source connected to the dummy bit line DBL1.
According to the example in FIG. 3, each dummy memory cell activated by the dummy word line DWL is therefore configured so as to set the two dummy bit lines DBL0 and DBL1 towards the ground, in other words to discharge them, these two dummy bit lines then being connected together at the input to the inverter of the control means MC provided to generate the activation signal.
To achieve this, the corresponding inputs of each inverter N4/P4 and N5/P5 in the dummy memory cell are connected to Vdd (high logical levels). Thus, the two internal nodes in the cell formed by the corresponding outputs of each inverter, have their value hard coded. Since the gate of the access transistors N2 and N3 is connected to the dummy word line DWL, when this word line is activated, the dummy bit lines DBL0 and DBL1 discharge through the transistors N3 and N5 and N2 and N4 respectively, that are then conducting.
In one variant, it is possible to use only a single side of the dummy memory cell, so as to use the discharge from a single dummy bit line to generate the activation signal Act. FIG. 4 shows such a dummy memory cell, that when it is activated by the word line DWL, is configured so as to set the dummy bit line DBL1 to the ground. To achieve this, the two inverters N4/P4 and N5/P5 are connected back to front and the input of inverter N4/P4 is looped back to the output from inverter N5/P5 and connected to Vdd. The two internal nodes of the cell formed from the corresponding outputs from each inverter, then have their value hard coded. Since the gate of the access transistor N2 is connected to the dummy word line DWL when it is active, the dummy bit line DBL1 discharges through transistors N2 and N4, both being conducting in this case. The other side of the memory cell is not used, the gate of the access transistor N3 then being connected to the ground Gnd.
Furthermore, in prior art, a delay circuit is usually provided in the dummy path and more precisely is integrated in the control circuitry MC, so that the time at which the signal to activate read amplifiers SA in the memory plane is output can be adjusted, so that the memory can operate correctly in all situations. Typically, an RC circuit or a logical gate is used to manage the delay composed of a plurality of inverters in series in order to delay output of the activation signal.
However, such a control to activate amplifiers to read the memory limits the possibilities of the memory being integrated. Firstly as explained above, it imposes that the value of the internal nodes of dummy memory cells activated by the dummy word line is hard coded, which is restrictive in terms of design rules for manufacturing the memory, and secondly special circuitry has to be provided in the dummy path, in fact the delay circuit, to be able to adjust the memory plane read amplifiers to optimise output of the activation signal. Furthermore, the delay thus generated by the delay circuit is not related to the discharge time of the bit line, therefore it has the disadvantage that it does not vary in the same way as the discharge from the bit line when faced with variations in manufacturing processes.
Embodiments of the invention are intended to overcome at least some of the above-mentioned disadvantages.